Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration ("VLSI"). The multilevel interconnects that lie at the heart of this technology require planarization of high aspect ratio features such as plugs and other interconnects. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Conventional chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques are used to deposit electrically conductive material into the contact holes and vias formed on the substrate. One problem with conventional processes arises because the contact holes or vias often comprise high aspect ratios, i.e., the ratio of the height of the holes to their width or diameter is greater than 1. The aspect ratio of the holes increases as advances in technology yield more closely spaced features.
Referring to FIG. 1, a substrate 10 includes a hole 11 formed within an electrically insulative or dielectric layer 12 thereon, such as for example, a silicon dioxide or silicon nitride layer. It is difficult to deposit a uniform metal-containing layer into the high aspect ratio hole 11 because the metal-containing layer often deposits on the sidewalls 14 of the holes and across the width of the hole to eventually converge across the width of the hole before it is completely filled, and thus forms voids and discontinuities within the metal-containing material. Thereafter, the high mobility of metal atoms, surrounding the voids causes the atoms to diffuse and minimize the surface area of the voids forming circular shaped voids as shown in FIG. 1. These voids and discontinuities result in poor and unreliable electrical contacts.
One method used to reduce the likelihood that voids will form in the vias is to "planarize" the metal at high temperatures. Formation of a continuous wetting layer on the substrate is the key for successful planarization at high temperatures. It has been discovered that a thin conformal aluminum film is a good wetting layer for subsequent physical vapor deposition and planarization techniques performed at high temperature (.gtoreq.350.degree.). This discovery is disclosed in co-pending U.S. patent application Ser. No. 08/561,605, now U.S. Pat. No. 5,877,087, entitled "Low Temperature Integrated Metallization Process and Apparatus" which was filed on Nov. 21, 1996, and is commonly assigned to Applied Materials, Inc. One method disclosed in that application is the use of a wetting layer deposited using chemical vapor deposition techniques, i.e., an aluminum layer, as the planarization wetting layer. It was believed prior to the present invention that to deposit a thin conformal wetting layer in the via, it was necessary to first deposit a conformal nucleation layer. The use of thin nucleation layers is disclosed in U.S. patent applications Ser. No. 08/620,405, pending entitled "Single Step Process for Blanket-Selective CVD Aluminum Deposition; U.S. patent application Ser. No. 08/622,941, pending entitled "Blanket-Selective Deposition of CVD Aluminum and Reflectivity Improvement Using a Self-Aligning Ultra-Thin Layer"; and U.S. Pat. No. 08/561,605, now U.S. Pat. No. 5,877,087, entitled "Single Step Process for Blanket Selective CVD Al Deposition", and commonly assigned to Applied Materials, Inc.
Another problem associated with Al interconnects is the formation of TiAl.sub.3 in applications where Ti is deposited as an underlayer before Al deposition. Ti has a propensity to bind Al and form TiAl.sub.3 which is an insulator thereby compromising the performance of an interconnect. One solution to prevent TiAl.sub.3 formation is to follow deposition of a Ti layer with deposition of a TiN layer. This reduces the amount of Ti available to bind Al. While this sequence provides a possible solution in some applications, as feature sizes decrease the need to reduce the thickness of any underlayers increases.
Thus, there is a need for a process to fill high aspect ratio contact holes and vias in a substrate without forming voids or defects in the deposited material. It is also desirable for the deposition process to deposit grains that are highly oriented in particular crystallographic planes.